library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;

entity MULTIPORT is
PORT
	(
--		Interface to PHY P1

		TX_EN_P1,TX_ER_P1		: OUT STD_LOGIC ;
		q_sig_P1			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdclk_sig_P1		: IN STD_LOGIC ;
		reset		: IN std_logic;				
-- 		Length FIFO signals to SF P1				
		wrclk: std_logic;
		wrreq_sig_L_P1		:IN STD_LOGIC;
		data_sig_L_P1:  STD_LOGIC_VECTOR (11 DOWNTO 0);				

--		Data FIFO signals to SF	P1
	
		data_sig_P1		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--		wrclk_sig_P1		: IN STD_LOGIC ;
		wrreq_sig_P1		: IN STD_LOGIC ;		
		wrusedw_sig_P1		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
------------------------------------------------------------------------------
--		Interface to PHY P2

		TX_EN_P2,TX_ER_P2		: OUT STD_LOGIC ;
		q_sig_P2			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdclk_sig_P2		: IN STD_LOGIC ;
--		reset_sig_P2		: IN std_logic;				
-- 		Length FIFO signals to SF P2				

		wrreq_sig_L_P2		:IN STD_LOGIC;
		data_sig_L_P2:  STD_LOGIC_VECTOR (11 DOWNTO 0);				

--		Data FIFO signals to SF	P2
	
		data_sig_P2		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--		wrclk_sig_P2		: IN STD_LOGIC ;
		wrreq_sig_P2		: IN STD_LOGIC ;		
		wrusedw_sig_P2		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
------------------------------------------------------------------------------
--		Interface to PHY P3

		TX_EN_P3,TX_ER_P3		: OUT STD_LOGIC ;
		q_sig_P3			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdclk_sig_P3		: IN STD_LOGIC ;
--		reset_sig_P3		: IN std_logic;				
-- 		Length FIFO signals to SF P3				

		wrreq_sig_L_P3		:IN STD_LOGIC;
		data_sig_L_P3:  STD_LOGIC_VECTOR (11 DOWNTO 0);				

--		Data FIFO signals to SF	P3
	
		data_sig_P3		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--		wrclk_sig_P3		: IN STD_LOGIC ;
		wrreq_sig_P3		: IN STD_LOGIC ;		
		wrusedw_sig_P3		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
------------------------------------------------------------------------------
--		Interface to PHY P24

		TX_EN_P4,TX_ER_P4		: OUT STD_LOGIC ;
		q_sig_P4			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdclk_sig_P4		: IN STD_LOGIC ;
--		reset_sig_P4		: IN std_logic;				
-- 		Length FIFO signals to SF P4				

		wrreq_sig_L_P4		:IN STD_LOGIC;
		data_sig_L_P4:  STD_LOGIC_VECTOR (11 DOWNTO 0);				

--		Data FIFO signals to SF	P2
	
		data_sig_P4		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--		wrclk_sig_P4		: IN STD_LOGIC ;
		wrreq_sig_P4		: IN STD_LOGIC ;		
		wrusedw_sig_P4		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
		


	);

end MULTIPORT;

architecture main of MULTIPORT is
--------------------data_FIFO-----------------------------
	COMPONENT transmit
	PORT (
--		Interface to PHY
		TX_EN,TX_ER		: OUT STD_LOGIC ;
		q_sig			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdclk_sig		: IN STD_LOGIC ;
		reset_sig		: IN std_logic;				
-- 		Length FIF signals to SF				
		wrreq_sig_L		:IN STD_LOGIC;
		data_sig_L:  STD_LOGIC_VECTOR (11 DOWNTO 0);				
--		Data FIFO signals to SF		
		data_sig		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wrclk_sig		: IN STD_LOGIC ;
		wrreq_sig		: IN STD_LOGIC ;		
		wrusedw_sig		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
	);
	END COMPONENT;
signal reset_sig_P1: std_logic;
signal reset_sig_P2: std_logic;
signal reset_sig_P3: std_logic;
signal reset_sig_P4: std_logic;

signal wrclk_sig_P1: std_logic;
signal wrclk_sig_P2: std_logic;
signal wrclk_sig_P3: std_logic;
signal wrclk_sig_P4: std_logic;

begin
-----------------------------------------		
PORT_ONE : transmit PORT MAP (

		TX_EN=>TX_EN_P1,
		TX_ER=>TX_ER_P1,
		q_sig=>q_sig_P1,
		rdclk_sig=>rdclk_sig_P1,
		reset_sig=>reset_sig_P1,
-- 		Length FIF signals to SF				
		wrreq_sig_L=>wrreq_sig_L_P1,
		data_sig_L=>data_sig_L_P1,				
--		Data FIFO signals to SF		
		data_sig=>data_sig_P1,
		wrclk_sig=>wrclk_sig_P1,
		wrreq_sig=>wrreq_sig_P1,
		wrusedw_sig=>wrusedw_sig_P1	
	);
------------------------------------------
PORT_TWO : transmit PORT MAP (

		TX_EN=>TX_EN_P2,
		TX_ER=>TX_ER_P2,
		q_sig=>q_sig_P2,
		rdclk_sig=>rdclk_sig_P2,
		reset_sig=>reset_sig_P2,
-- 		Length FIF signals to SF				
		wrreq_sig_L=>wrreq_sig_L_P2,
		data_sig_L=>data_sig_L_P2,				
--		Data FIFO signals to SF		
		data_sig=>data_sig_P2,
		wrclk_sig=>wrclk_sig_P2,
		wrreq_sig=>wrreq_sig_P2,
		wrusedw_sig=>wrusedw_sig_P2	
	);
--------------------------------------------	
------------------------------------------
PORT_THREE : transmit PORT MAP (

		TX_EN=>TX_EN_P3,
		TX_ER=>TX_ER_P3,
		q_sig=>q_sig_P3,
		rdclk_sig=>rdclk_sig_P3,
		reset_sig=>reset_sig_P3,
-- 		Length FIF signals to SF				
		wrreq_sig_L=>wrreq_sig_L_P3,
		data_sig_L=>data_sig_L_P3,				
--		Data FIFO signals to SF		
		data_sig=>data_sig_P3,
		wrclk_sig=>wrclk_sig_P3,
		wrreq_sig=>wrreq_sig_P3,
		wrusedw_sig=>wrusedw_sig_P3	
	);
--------------------------------------------
------------------------------------------
PORT_FOUR : transmit PORT MAP (

		TX_EN=>TX_EN_P4,
		TX_ER=>TX_ER_P4,
		q_sig=>q_sig_P4,
		rdclk_sig=>rdclk_sig_P4,
		reset_sig=>reset_sig_P4,
-- 		Length FIF signals to SF				
		wrreq_sig_L=>wrreq_sig_L_P4,
		data_sig_L=>data_sig_L_P4,				
--		Data FIFO signals to SF		
		data_sig=>data_sig_P4,
		wrclk_sig=>wrclk_sig_P4,
		wrreq_sig=>wrreq_sig_P4,
		wrusedw_sig=>wrusedw_sig_P4	
	);
--------------------------------------------
reset_sig_P1<=reset;
reset_sig_P2<=reset;
reset_sig_P3<=reset;
reset_sig_P4<=reset;
wrclk_sig_P1<=wrclk;
wrclk_sig_P2<=wrclk;
wrclk_sig_P3<=wrclk;
wrclk_sig_P4<=wrclk;
end main;
